1. Field of the Invention
The invention generally relates to electronics. In particular, the invention relates to phase locked loop (PLL) and delay locked loop (DLL) circuits.
2. Description of the Related Art
It is common in electronics to use high speed (multi-GHz) clock phase generation, frequency multiplication (clock synthesis), and/or clock and data recovery. The PLL (phase locked loop) is an efficient and modern technique to implement these functions. An example of a conventional PLL is illustrated in FIG. 1. The illustrated PLL is a feedback loop system in which the input clock signal 102 (can be embedded with data) is discriminated in phase by a phase detector 104 with respect to a feedback clock signal 106 and further processed through a loop filter 108 and a voltage-controlled oscillator (VCO) 110. In the diagram, capacitance for the charge pump (QP) 114 is included in the loop filter 108.
The phase detector 104 includes a phase frequency detector (PFD) 112 and a charge pump (QP) 114. Advances in PFD 112 design have not kept up with advances to VCO 110 design, as reference clock input requirements have typically remained low. However, the absence of advancements has prevented the use of PLLs with relatively high-speed signals.
FIG. 2 illustrates a conventional implementation of a phase detector comprising a 3-state phase frequency discriminator (PFD) 112 and a charge pump (QP) 114. The PFD 112 includes flip-flops 202, 204 and an AND gate 206. The charge pump (QP) 114 includes current sources 210, 212, switches 214, 216. The loop filter 108, can include capacitance for storing charge for the charge pump (QP) 114. A switch 214 or 216 is closed when the output (up signal 203 or down signal 205) of the corresponding flip-flop 202 or 204 is high. The up signal 203 and the down signal 205 are control signals. The up signal 203 is high for longer than the down signal 205 is high when the input clock signal REF_CLK 102 is leading the feedback clock signal FB_CLK 106. Conversely, when the input clock signal REF_CLK 102 is lagging the feedback clock signal FB_CLK 106, the down signal 205 is high for longer than the up signal 203. The operation of the switches controls the charge accumulated by the loop filter 108, and the resulting voltage across the loop filter 108 controls the VCO 110. A problem that plagues the conventional implementation is shown in FIGS. 3A and 3B.
A reset signal 207 is generated by the logical AND 206 of the UP signal 203 output of the UP flip-flop 202 and the DN signal 205 output of the DN flip-flop 204. As illustrated in FIG. 3A, a pulse of the reset signal 207 has a finite, non-zero, width trst, i.e., cannot be infinitely small. As frequencies increase, the width trst of the reset pulse begins to intrude into the linear range of operation. As illustrated in FIG. 3B, at high frequencies, the width trst of the pulse of the reset signal 207 converts the intended asymmetrical behavior of a three-state PFD 112 (shown by dotted lines) into a symmetrical two-state phase detector (bold solid lines), which is detrimental to the frequency locking process.
The conventional art describes two approaches to using a PFD 112 at high frequencies. One approach reduces the width of the reset pulse. A second approach reduces the gain (KPD) of the phase detector 104 beyond a certain phase difference. Both approaches will be discussed below.
Reducing the pulse width trst of the pulse for the reset signal 207 of the PFD 112 has many implications. For shorter pulse widths trst, the switches 214, 216 of the charge pump (QP) 114 should be faster. In addition, faster or advanced logic styles may be needed. See, for example, U.S. Pat. No. 7,053,666 to Tak, et al. There is a limit to how narrow the pulses from the PFD 112 can be because the charge pump (QP) 114 uses a finite amount of time to switch ON or OFF and will be unresponsive if not provided with at least the minimum amount of time. Furthermore the PFD 112 should also detect instances of missing edges across a wider zone. See, for example, Mansuri, et al., in Fast Frequency Acquisition Phase-Frequency detectors for G-samples/s Phase-Locked Loop, IEEE Journal of Solid State Physics, Vol. 37, No. 10, pp. 1664-1334, October 2002; U.S. Pat. No. 5,892,380 to Quist; and U.S. Pat. No. 7,053,666 to Tak, et al.
The gain (KPD) of the phase detector 104 can be reduced for missing clock pulses. FIG. 4 illustrates a simulation of a transfer characteristic of an ideal PD, non-ideal PD, and a PD with a flat gain. Typically, the gain is reduced to no gain. This reshaping of the transfer characteristic avoids the problem of gain reversal shown in FIGS. 3A and 3B. The gain reduction can be implemented by generating a small pulsed signal. See, for example, Mansuri, et al., in Fast Frequency Acquisition Phase-Frequency detectors for G-samples/s Phase-Locked Loop, IEEE Journal of Solid State Physics, Vol. 37, No. 10, pp. 1664-1334, October 2002 and Centurelli, et al., Robust three-state PFD architecture with enhanced frequency acquisition capabilities, Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS) 2004, Vol. 4, May 23-26, 2004, pp. 812-15.
Reducing the gain (KPD) of the phase detector 104 can have implications. To trigger one of the flip-flops 202, 204 (FIG. 2), a small pulse is generated at an input clock of the corresponding flip-flop 202, 204. The gain reduction technique adjusts the delay between the reset pulse with respect to that of the trigger to the flip-flops 202, 204. This delay can be sensitive to various process, voltage, and temperature (PVT) variations, on the rise and fall time of the clocks, and is typically limited to implementations of only high-speed logic families.
The small pulse should be smaller in width than the width of the reset pulse or the PLL can fail to lock at zero phase difference. This mandates even faster switching of the charge pump (QP) 114, or there can be zones of no response from the PFD-QP combination. The gain reduction technique can still result in partial output polarity reversal.